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Freescale Semiconductor /MKE18F16 /WDOG /CS

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Interpret as CS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)STOP 0 (0)WAIT 0 (0)DBG 0 (00)TST0 (0)UPDATE 0 (0)INT 0 (0)EN 0 (00)CLK0 (0)RCS 0 (0)ULK 0 (0)PRES 0 (0)CMD32EN 0 (0)FLG 0 (0)WIN

WAIT=0, CMD32EN=0, CLK=00, ULK=0, TST=00, STOP=0, UPDATE=0, INT=0, WIN=0, DBG=0, FLG=0, RCS=0, PRES=0, EN=0

Description

Watchdog Control and Status Register

Fields

STOP

Stop Enable

0 (0): Watchdog disabled in chip stop mode.

1 (1): Watchdog enabled in chip stop mode.
WAIT

Wait Enable

0 (0): Watchdog disabled in chip wait mode.

1 (1): Watchdog enabled in chip wait mode.
DBG

Debug Enable

0 (0): Watchdog disabled in chip debug mode.

1 (1): Watchdog enabled in chip debug mode.
TST

Watchdog Test

0 (00): Watchdog test mode disabled.

1 (01): Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.

2 (10): Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].

3 (11): Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
UPDATE

Allow updates

0 (0): Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.

1 (1): Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
INT

Watchdog Interrupt

0 (0): Watchdog interrupts are disabled. Watchdog resets are not delayed.

1 (1): Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
EN

Watchdog Enable

0 (0): Watchdog disabled.

1 (1): Watchdog enabled.
CLK

Watchdog Clock

0 (00): Bus clock

1 (01): LPO clock (128k LPO, 32k LPO, 1k LPO, or 32k OSC), whose selection is controlled via SIM_LPOCLKS[LPOCLKSEL].

2 (10): System oscillator clock (SOSC, from SCG)

3 (11): Slow internal reference clock (SIRC, from SCG)
RCS

Reconfiguration Success

0 (0): Reconfiguring WDOG.

1 (1): Reconfiguration is successful.
ULK

Unlock status

0 (0): WDOG is locked.

1 (1): WDOG is unlocked.
PRES

Watchdog prescaler

0 (0): 256 prescaler disabled.

1 (1): 256 prescaler enabled.
CMD32EN

Enables or disables WDOG support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words

0 (0): Disables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words

1 (1): Enables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words
FLG

Watchdog Interrupt Flag

0 (0): No interrupt occurred.

1 (1): An interrupt occurred.
WIN

Watchdog Window

0 (0): Window mode disabled.

1 (1): Window mode enabled.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data